With the appropriate pipelining, I think you should be able to get it done as fast as your acquisition comes in. Of course, the time for the data to be acquired, processed and output will be the same in total, but you could acquire new data as fast as your module (rather than as fast as your module acquisition period + processing time).
Perhaps the simplest (although not necessarily the fastest) way to do this is to put acquisition in one loop, local FIFO to a SCTL or if needs must a While loop, then just check for valid data (handshaking) or non-timeout (timeout) to process.
Like Intaris said (and I tried to say, perhaps unsuccessfully), it seems like you have lots of separate loops and it's not obvious why this should be the chosen design...
