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Re: Data socket exe build error

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Harlequinade,

 

You're right. It seem like i have problem with icon creation even i use other NI examples, it will prompt error.

When try to open the icon.llb & open "read icon for Application.vi / EXE.vi", it will looking for "draw flattened pixmap.vi" & missing "flattened pixmap.vi" too.

Any possible where to download the icon.llb?

Thanks,

Simon

 


Re: Programmatically Read Y Values For A Multiplot Cursor

Re: FPGA timing different in execution mode and simulation mode

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A little update to the topic - I created an application where I can disable parts of the code through the Case structure and check for timing. First, I fully understand that adding ten new case structures affects the execution a lot. But still, outcome is unexpected:

 

Everything disabled: 10 ticks per loop

Enabling FIFO writes (9 elements): 36 ticks per loop

Also enabling filters: 75 ticks per loop

Also enabling flagging (custom bitwise data manipulation): 105 ticks per loop

Also enabling input reading: 782 ticks per loop

Disabling everything but input reading: 392 ticks per loop

 

After enabling input reading, loop is timed by input signal (which runs at 392 ticks per one sample). It is like enabling input reading slows everything down about 6 times. Any ideas now?

Thomas444_0-1580739561823.png

Re: FPGA timing different in execution mode and simulation mode

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Hi Thomas,

 


 wrote:

After enabling input reading, loop is timed by input signal (which runs at 392 ticks per one sample). It is like enabling input reading slows everything down about 6 times. Any ideas now?

 In your first message you wrote:

I use a while loop to read inputs of 3 x NI 9232 in cRIO 9057 @ 102400 Hz, which means 9 channels.

The FPGA runs at 40MHz, divided by 102.4kHz gives 390.625 ticks per sample, pretty close to your 392 ticks per while loop iteration. Pure coincidence?

Re: Get data type icon for use in tree control

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SuperSecretPrivateSpecialStuff=True


That sound like you just made it up. LOL

Re: FPGA timing different in execution mode and simulation mode

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Exactly, I point that out from the beginning. But processing by itself takes ~ 100 ticks when in execution mode, so it should always be done 392 ticks. Which it isn't. It takes double of that period, ~ 790 ticks. See?

 

Edit: Now I have an idea. Maybe, maybe the data from multiple channels of every module are not ready at the same instance. That would mean that every sampling cycle is divided in thirds (for 3 channels) and processing starts only in the last third, after all three channels are ready for dispatch. That might explain why ~ 100 ticks of processing cause doubling the timing when combined with reading the inputs. I will try making another application where I can disable certain channels. Also, using FIFO might fix this.

ERROR 4803 cause my "Sound File Read Simple.vi" error

Re: FPGA timing different in execution mode and simulation mode

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Your code does not run in parallel. Your inputs need to complete running before the rest can even start.

 

If this code would be ALL in a SCTL (not just portions of it - I do not understand why your FIFO writes are in SCTLs for a single element) then the code would be executed in a far more efficient manner.  Each node you add to your code slows your overall execution down by that much. Only one portion of the code is ever active at once when you are not using SCTLs. So if ONLY your inputs cost 392 ticks, that's the minimum you're going to need. Every single other operation you add will increase that time (and can't be run in parallel due to data flow).  I think your IO may be synchronising with hardware each time you start executing the node. Your loop timing is suspisciously close to exactly 2x the IO Node timing itself. Because you only start reading a new value 100 ticks after the last one completed, you may "miss" a cycle depending on how the IO node works internally. It's pretty much a guess, but it seems to fit your descriptions.

 

I recommend reading:

http://download.ni.com/pub/gdc/tut/labview_high-perf_fpga_v1.1.pdf

 

Page 15&16.


Re: ERROR 4803 cause my "Sound File Read Simple.vi" error

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Hi guy from China,

 

I guess the problem is in your WAV file.

Unfortunately all we got is an image with the error message, but not the WAV file itself…

Re: Data socket exe build error

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Pfff, I don't know where you would be able to download it.

 

I guess I would recommend you to repair your LabVIEW installation. You can start that under the uninstallation options. It takes a while, so start it before lunch / going home.

Re: ERROR 4803 cause my "Sound File Read Simple.vi" error

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You got Chinese characters in the folder name and filename.

Have you tried a full English path?

 

Re: Sound acquiring using myRIO's Audio in port

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Thank you for your reply No it doesn't. what confuses me most is that the preamp. has a +50 dB gain

Filemaker Pro ODBC

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I wanted to connect to ODBC in Filemaker. When going to add DSN "Filemaker ODBC" did not show up. I had to download  "FM18_xDBC_18.0.1.exe". When I ran this program it flashed and disappeared. Apparently is justed unzip to the same directory and made a folder "FileMaker 18 xDBC\ODBC Client Driver Installer" in that folder is 2 installers, FMODBC_Installer_Win32, FMODBC_Installer_Win64. The both need to be install appartently according to "https://www.youtube.com/watch?v=8T_M8lDwGg0"  here is a guide to finishing. "https://fmhelp.filemaker.com/docs/edition/en/fm_odbc_jdbc_guide.pdf"

 

more later

Cursor to indicate a plateau

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Hello all,

I have a trapezoidal force trajectory and have a Cursor.PosX which is supposed to indicate the end of the plateau and have been told to create an Active Cursor to indicate the beginning of the plateau. I am a true beginner and am being led through this with few instructions. I am using labview 2017. I'm sure its relatively simple but I haven't found an answer in my searches on search engines, this forum, and the stickys here. I have attached my vi. Please let me know if I can answer any questions or if you have some good resources for beginners!

Re: Learning with LabVIEW, Robert H. Bishop example VI's


Re: Re : Insert image file to word document using active X

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Hello,

 

many thanks for this code, I'm looking for something similar. My problem is that I have a folder with lot of pictures and I would like to insert into a word document them.

 

This VI is opening and inserting only one picture into word right? Is it possible to modify to more pictures which are in a same folder?

 

Thanks and best regards,

Gabor

Stereo sound generation

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I have been looking for an example that will allow me to generate two different tones right and left channel using a sound card.

 

All of the examples I can find generate a mono signal of the exact same frequency and amplitude on both channels.  The Sound Output Configure.vi lets you pick one or two channels but if I select one channel what channel is selected right or left? How do I select the Right channels for a 1khz tone and the left channels for a 5Khz tone?

 

BTW: I need to generate the tones not playback a waveform or recorded stereo sound file

Re: linear fit

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 wrote:

Could you help me with this part? 

There is a ptbypt version of array min&max, so use that. Note that the first slope is NaN (because we only have 1 value!), so you need to initalize on the second iteration. Also note that you might want to ignore the first results, because they don't rely on a full set of values, so initialize min&max if e.g. i=59 or similar.

 

This will give you the slope, not the "angle", so add a little trigonometry. I trust you can do that.

 

 

altenbach_0-1580746543473.png

 


 wrote:

Then I would like to write these values (max and min) in an external file. 


There are millions of ways to write two values to a file. What have you tried?

 

 

Re: Cursor to indicate a plateau

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Your VI is broken because you have an unwired terminal.

 

You need to wire a constant into Active Cursor to tell it which cursor you want to make active.  You should also put the active cursor line on that property node above the Cursor.PosX property.  Property nodes execute from the top to the bottom.  You need to tell it which cursor you want to make active before you request the PosX data from it.

 

You should put a small wait function in that loop so it isn't burning up your CPU doing the same calculations as fast as ti can.

 

I would recommend looking at the online LabVIEW tutorials
LabVIEW Introduction Course - Three Hours
Learn LabVIEW

 

 

Re: FPGA timing different in execution mode and simulation mode

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Also,

Take the FP boolean controls out of the processing IO loop. Put them in another loop, and use local variables to read the booleans in the time critical loop.

 

Sounds bizzare, but years ago NI R&D offered this when we had timing, issues with time critical loops. The reason is the FP control in the Time critical loop - requires overhead to check if it's value has changed, this chews up processing.

A local variable essentially, puts a wire between the two loops - and decouples the TC loop from determining is the boolean value has changed on the FP.

 

Also, any filter will create some latency, as they all essentially buffer data and do summing and/or divsion. It would be better to put an actual filter circuit on the wire instead. I am working on a PID project now, where we are having a latency issue with the filter and are solving it that way.

 

Regards

Jack Hamilton

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