Hi Steffen,
Does it really compile everything?
Yes, LabVIEW is executing compiled code - always!
Could there be issues with identical names for vis?
Not that I heard of…
Or names like [RT] Main.vi?
Not that I heard of…
Could it be, startup.rtexe cannot find something?
Then it would not run at all - or should give proper error messages you can handle in your code!
when I deploy it from Labview, it actually works?
That's the point why you should deploy your RTEXE from the IDE!
Did you check the memory usage of your application over time?
It's also possible that some piece of code kept messing up mildly with the process memory until it crashed (wrong memory allocation on function calls).
Yet it's peculiar that some other parts of program are still running.
I attached a picture, so you can see, the event is available 
I understand your point, there is a lot of private LabVIEW API, but in this case it is not true, because it is used by DETT. As I mentioned, it is not "totally" public API, because it can be enabled only with a special flag, but as far as I know, it is not forbidden to use it. The question is still; does the code available behind Application.DTT.Setup, which is responsbile for subscribe to "VI Execution High or Low Level" events?
The checksum is calculated here
Alles klar!
Hi Gerd,
Thank you !!
Am just checking the data transfer with the code, from target to host.
As an example to be tried out, i just split and joined the numbers so that, I can identify how exactly the CLIPS show data after connecting them through Data lanes. Hence, the need..
Thanks so much, I got my goal with your solution.
Oops, make that a cRIO 9068, not a 9065.
I know it must be a basic thing...
I just want to view a list of all posts there Started by me on this support forum !! I remember being able to do this some time ago but now forgot how. ( Only posts that are started by me and not posts to which i responded )
Thanks for any help !
I have try to build a string according to 8 cases. I have a numeric array which has 0 to 8 elements. The array size is not fixed, it can be change. However that 8 cases are settled.
Case for 0; "Pin=0"
Case for 1; "Pin=1"
Case for 2; "Pin=2"
...
Case for 7; "Pin=7"
array example is like that,
[0]
[2]
[4]
[7]
the string I want like this,
Pin=0
Pin=2
Pin=4
Pin=7
Click on your icon, you will be directed to your profile page. The upper list on the right is your "Most recent posts". Clicking on the little arrow on the right (actually a > ) you can see the complete list of your posts.
Its the "> " that I was after ... thanks for pointing it out !!
Hi , the interesting thing is that : when i pulling the CS low , and measuring the voltage , i still measure 3.3V , insted of GND .
Hello all,
I'm currently building an application featuring RT/FPGA code, Web Service and a Web Page front panel. All this run on a sbrio 9637, and I've some issue with the performance. My Labview code doesn't use much cpu performance, but I have a lot (?) function in my webservice (around 60), and some are called very often (I have permanently around 3 light [memory read and transmission, small amount of data] Web Service called at least 3/4 time every second). With my webpage being hosted on the sbrio, I reach a very high use of the two cores (85%+) and all my system rapidely slow down.
I didn't find much info concerning the performance of the webservice/webhosting. So my first question is : All my functions are inside only one WebService. Should I separate them ? Would this be worst of best relative to the performance ?
What do I need to know concerning the limit of hosting a webpage on such a device ? Opening a Webpage, even one without any kind of communication use up a lot of cpu.
All of my critical code is inside the FPGA, outside, I have "classic" code, using known mechanism which are not RT because they don't need to be (temporised while loop and queue to transmit orders between loops). But with time passing, everything get seriously slow (like : 0.2s reaction time in the beginning, and 10s after 5h, I'm forced to reboot), and I have no idea why. I know it's a very open question since I'm not submitting you a lot of element, but if anyone have ideas concerning this general slowdown I'll take it.
Thank you in advance
but then the cRIO can never run without Labview, because rtexe does not execute on bootup? cRIO should be able to run on its own.
I guess I put some markers into that Main vi tomorrow, see how far it executes.
Hello ! i am sending serial data to my labview application from hyper terminal at baud rate of 9600 bps , i am displaying that data after concatenation at a string indicator but when i send the same character consecutively then i am not getting proper representation at the receiving side.
the screenshot of the problem is posted below.
I strongly recommend the followin order of Invoke nodes when starting the FPGA bitfile:
This will abort the perhaps already running FPGA bitfile, which is necessary to download and start a new bitfile.
About VI-file names in an rtexe:
In my company we had some issues with VI-names when they contained special characters like german umlaute. As long as you stick to ASCII-Code there shouldn't be a problem.
Identical VI-names can be an issue if you set the option "Use LabVIEW 8.x file layout" under "Advanced"-options. If this option is not set there shouldn't be an issue with identical vi-names.
Regards, Jens
Hi Steffen,
to add to Jens' suggestion:
I'm using this code to start FPGA on several cRIO chassis for years without any problems at all…
Hi! I'm sorry my Supervisor told me I'm not allowed to upload the code online, though I don't think what I'm doing is classified.
Anyway I have successfully built the convolution with fixed size Array. However the Problem is that I'm trying to build discrete wavelet transform which contains decimation of the samples. So basically, at the end of the For Loop, I need to discard half of the samples and return the half size Array to the beginning. So the shift Registers at my For Loop have different size and the fpga does not allow this. That's my problem now.
Thank you!
Hi rwthybw,
I need to discard half of the samples and return the half size Array to the beginning. So the shift Registers at my For Loop have different size and the fpga does not allow this.
You could:
- replace half of the array elements by zeros…
- reorder the needed array elements to the first half of your array and replace the second half by zero…
- use a 2nd shift register to keep the half-size array
All those options boil down to: you have to work with fixed-sized arrays!
