The error is in "cofigure serial port", way before the string operation. Make sure all inputs there are valid. How do you define the visa resource?
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Re: how to convert a number into an ascii code
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Re: FPGA: unpacking U32 into bits causes fan-out timing violation
Your 32bit greaterorequal is costing a lot of time. Is this really neccessary?
Can you post a screenshot of the compile error?
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Re: Read file or folder name when I press the mouse button over it !
HIi Crossrulz and Altenbach,
Jus consider that I want to read folder name, that is available in the desktop. When I make a click over the folder (you can see in below desktop picture), LV shld read the folder name and store it in an array. Front panel picture shows the simplified idea about the VI. Hope I clear you about my query !!!!!!
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Re: rearrange 2 d array into ascending order
Thanks for the replys,
i have created the code that you had shown and it is arranging the data in not just asceding order of the first column but alsothe second column.
you can see from the orignal data that the first occurence of channel 0 is in the second row, its data is F32. F32 should be a the top of the newly arrange data, but as it is arranging both by ascending order it is in the 98th row.
ive attached a vi of the dta im receiving
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Re: FPGA: unpacking U32 into bits causes fan-out timing violation
Ok, sorry, I've found a way to access DIOPORT0 on both connectors. Attaching the new version.
However, there's still a timing violation. Also attached.
The greater-than-or-equal is used to decide whether it's time to output the new digital levels.
Any suggestions will be appreciated.
Itay.
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Re: FPGA: unpacking U32 into bits causes fan-out timing violation
It seems like your "Greater or equal" is costing a lot.
It seems like you're sending data from the host via DMA FIFO and are using the first 32 bits as some kind of signal when to stop. Can you not replace this with a single boolean to signal the endof the data? Even comparing to 0 is relatively expensive for a 32-bit number. Switching to a simple boolean (for example, first byte of the input data instead of the whole 32-bit number).
You can then send a "stop" signal as a simple boolean from the host to tell the loop when to stop.
The "fan out" error is an optimisation problem of the xilinx compiler and has nothing to do with the "fanout" of your 32-bit number to the digital outputs.
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Re: Single Cycle Time Loop
Yes this does seem strange. Can you show us your code?
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Re: Built classes directly into an exe for dynamic loading. But now the installer builder claims that the files can't be found in the built exe?
I posted a picture of my destinations here. Hopefully there's something trivial wrong with the way I defined them that you could point out?
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Re: LabVIEW load error code 3
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Re: Single Cycle Time Loop
I have attached both of FPGA VIs. The hardware is sbRIO-9626.
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ecg gap in waveform chart
Hi, i've got a problem with my project about ecg. I want visualized an ecg signal using labview and my soundcard of pc, but when i start my project there are some gaps on my chart. What is the problem? i have to increase the number of samples/sec?.
i attached my .VI in this message. Thanks to everyone.
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Re: rearrange 2 d array into ascending order
From the help file for the Sort 1D Array function:
If array is an array of clusters, the function sorts the elements by comparing the first elements. If the first elements match, the function compares the second and subsequent elements.
This is expected behavior.
To do what you requires more complicated tracking of positions of data in the array. I do not have time now to put together an example.
Lynn
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Disable button using Property Node
I have used a button which counts as the button is pressed again and again, I want this button to get disabled when it counts till 6. I have used a case structure, which compares the value when it is greater than 6, it gets true value and the case structure should disable the button, but as I run the code the button is disabled already.
Can someone please guide me, where I have done mistake.
Regards,
Ather
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Re: Disable button using Property Node
You need to put another property node before the loop to enable the Top button before the loop starts.
Lynn
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Re: Labview exe running on development computer but it is broken on client computer
Typically it means you're missing some component on the target, as .net, visa or some thing you're making use of. So what do you make use of?
/Y
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Re: rearrange 2 d array into ascending order
Try this.
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Re: DAQ Card Assistant. URGENT.
You are sending an array of three booleans, but the DAQ assistan3 is only configured for one.
Well, you should probably start with one of the desing templates and do a proper state machine architecture. Why are there so many sequence frames in the sequence structure (For example the execution order of the code in the first three frame is irrelevant, so why chop up the dataflow?)? I would not trap the code with 60 seconds waits. Keep the program interactive!
Sorry, I hate express VIs and dynamic data, because they obscure way too much. I personally don't use them, so I am not sure what you get if an output tunnel uses default if unwired. I would probably use lower level DAQ and more defined datatypes for clarity.
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Re: rearrange 2 d array into ascending order
l_m_s wrote:
i have created the code that you had shown and it is arranging the data in not just asceding order of the first column but alsothe second column.
The problem is that you are dragging the entire array through the sorting mechansims, while it should only see the first column. If you do it as follows, the rows are sorted by the first column, leaving the second column in original order (note that the second cluster element is array index in the original array, so it is sorted by that if duplicates in the first column occur. That's apparently what you want.
(Note that the the overall logic is probably similar to what AYanez posted above, it just uses much less code and is more efficient. (see my signature! 
)
See if this works for you. Good luck!
I also strongly suggest that you don't parallelize these tiny loops. The bulk of execution time is spent sorting, and rattling through simple arrays is ~infinitely fast. Most likely the parallelization overhead is high in comparison and you'll not gain anything. It might actually slow you down. Note that the sorting itself if much faster in my code, because the cluster structure is much simpler.
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Re: Single Cycle Time Loop
Does the code with the SCTL actually work? It seems to me that most code is unreachable because the first SCTL never completes. All it does is repeat the same operation, and since it never produces any output, everything is probably optimized away, leaving you with basically an empty diagram.
Try wiring a TRUE to the termination conditions of the SCTLs and see what happens. (see also here)
("Single cycle" does not mean that it executes only once. It means that the code in it needs to complete in a single FPGA tick so the loop can spin at the FPGA clock rate.)
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Re: Single Cycle Time Loop
Yes, the SCTL will cause your usage to go down. The reason is that the SCTL causes LabVIEW to remove a bunch of buffers inside of the loop. It can do this since all of the code inside of the loop will execute in a single FPGA clock cycle.
Your code with the SCTL will not work as is. You need to wire in a TRUE to the termination for all of your SCTL. Also, you have a rotate array inside of a SCTL, which won't work.
Quickly looking at your code, you should be able to use just a singe SCTL to encompass all of your code (instead of your big while loop). You just need to work around those Rotate 1D Arrays. That is simple enough by keeping track of which element you want to replace. So instead of rotating the array, you just circularly replace a different element. We might also have to work around the FOR loops that add up your fixed point numbers. I have other thoughts for that, but not formulized enough right now to put down.
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