Re: FPGA Loop Timer Runs Unchecked When Executing on Development Computer

Hi Wes1s, 

You can still run your code using simulated I/O without using a Desktop Execution Node. This allows you to make sure the logic of your code is correct. In earlier versions of LabVIEW, simulated time more closely resembled wall clock time but it was not strictly the same as desktop computers are not capable of the speeds an FPGA is. The article below discusses the various options for debugging FPGA code. As shown in the table, running the FPGA in simulation mode only verifies the timing of code contained in a single-cycle timed loop. To verify all timing, you need to run the code on the FPGA or use a 3^rd party simulator.

http://www.ni.com/tutorial/51862/en/

Best,