How does the signal look like exactly?
There seems to be no detailed specifications on the signal form in order to be counted correctly (rising/falling time, minimum time to stay at a level (H, L), overshots, ...).
As the internal clock of the device is 100MHz, the decive can handle signals with 5ns H/L time, at least internally. But as generation is limited to 25MHz, it is possible that it is limited to 20ns....
In reality, i would expect the device to be somewhere in between these two numbers if the signal is "perfect" TTL/CMOS signal.
Norbert
