Dear Alex,
Thanks for your reply. I am a bit confused now. This page http://www.ni.com/white-paper/7299/en/ describes the ethercat protocol and states that each station reads from the ethercat train, while streaming the ethercat train to the next station. So, each station has access to the data on the ethercat train, therefore I would expect that all FPGAs have access to the ethercat train. So a few more question come to mind:
1. Why would the master controller be different?
2. Are the I/O of the master on the ethercat train?
3. If all NI9144 modules act as described in that white-paper, how do I then access the ethercat train in a second NI9144 to access I/O-data that was placed in the ethercat train by the first NI9144?
Cheers,
Frans