Hi P@Anand
Thank you very much for answer.
First of all we understand that we will not be able to skip the compilation. Project has to go through "Start Compilation" and "Generation of Intermediate Files" (see: http://www.ni.com/white-paper/9381/en/ for details). Our objectives that on these two steps our VHDL code will stay untouched by LabView compiler. And intermediate files that came to Xilinx Analyzer-Synthesizer-Mapper-Placer/Router will include our original VHDL code without any additions/modifications from LabView Compiler. Basically we want all logic implemented in the same way (or as close as possible) as if it was processed by Xilinx ISE for custom FPGA without LabView compiler "middle man".
Desire to implement code in VHDL approach based on assumption that LabVIEW "converter from VI to VHDL code" is not ideal and have some issues (see: http://www.ni.com/tutorial/14536/en/ for example) that potentially may introduce risk to operation of our system. This does not mean that LabView FPGA will not work; we just want to minimize risk by decreasing amount of intermediate processes at the same time we would like to have convenience of quick design with LabVIEW and NI hardware. (It is not so easy to find or design system with customable FPGA on board with 20-30 simultaneously sampling Analog Inputs, Analog Outputs and DIO that can easy transfer data and controlled from GUI)
Another reason for our approach is that we already have part of logic implemented in VHDL code, so we do not want to rewrite it in LabVIEW FPGA.
