Another guess - you have DMA communication between the RT and FPGA parts and you set a long or infinite timeout on that read or write operation. In normal LV, this would cause a reduction in CPU usage, because the code would wait for an interrupt to continue. In the case of a DMA read, it causes high CPU usage.
Generally, for debugging CPU consumption issues it is helpful to start disabling parts of the code. You do this until you find that the consumption is down and then you know which part is responsible. Another variation on this is to use case structures with boolean controls, which then allow you to dynamically play with this.