Try using a timed loop rather than a while loop on your FPGA diagram. You are not generating samples at a regular internval inside of a while loop, but inside of a single cycle timed loop you will. See the 'High-Performance Programming With the Single-Cycle Timed Loop' section that starts on page 15 of the High-Performance FPGA Developer's Guide for an in depth explanation.
The NI LabVIEW High-Performance FPGA Developer's Guide