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Re: [fpga] Faster communication between FPGA and real-time host

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dan_u,

 

I first tried using DMA FIFO, but found it to be inefficient for transferring single point data. Even with DMA FIFO, my rate was just 10 kHz (loop rate).The time taken by RT to just read the FIFO was around 40 us. I am very curious, and would like to know  how you are getting 8 us. I am attaching a screen shot of my RT program. It would be great if you can compare it your program and tell me where I have gone wrong. I appreciate your help.

 

P.S. FIFO_rms is the name of the FIFO, and I couldn't reduce its depth below 512.


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