RavensFan,
Thanks for the quick response. Yes, the picture didn't turn out as expected. I stripped out the loop in question from the FPGA code and posted it here. I am able to get as far as your suggestion but can't get further. I want to know if the the DIO are fired in a consistant manner or if there are delays. I had thought I could read the 64 bit word and if there is a change record it and the counter in memory. After I shut off the loop I want to read the memory and store it for later analysis by hand. This is a temporary piece and will be removed after the timing is established.
Thanks again.